cole mayke

portfolio, case studies, and engineering work

  • Cole Mayke profile photo
    my hardware work spans mixed-signal ic design, physical verification, rtl, and fpga systems.
    these case studies focus on architecture, simulation, and verification results.

projects / hardware

hardware engineering work

This track covers the semiconductor and digital-systems side of my work, from analog block design through verification and hardware-software integration.

featured

featured projects

Cadence Virtuoso PGA schematic from the mixed-signal ECG front-end showing the switched-capacitor gain path and supporting circuitry.

electrical engineering / mixed-signal ic design

Mixed-Signal ECG Front-End IC

problem

How do you acquire low-amplitude ECG signals and digitize them on-chip under a strict 1 V, low-power constraint?

Cadence VirtuosoSpectreVerilog-Amixed-signal simulation

what i did / what shipped

I designed and verified the analog chain end-to-end, from mux and PGA through op-amp and SAR ADC, then documented the final system in a full report.

Cadence layout of the common-source amplifier showing final placement and routing before post-layout verification.

electrical engineering / physical design

Analog Front-End Layout & Verification

problem

How do you carry an analog design through layout, DRC, LVS, and extraction without losing the behavior that mattered at schematic level?

Cadence VirtuosoCalibrefull custom layoutpost-layout analysis

what i did / what shipped

I completed layout, rule closure, extraction, and post-layout comparison so the design was validated as both geometry and electrical behavior.

supporting

supporting projects

electrical engineering / digital systems

AES-128 SoC Coprocessor

A memory-mapped AES-128 coprocessor verified against NIST vectors in simulation and exercised through the HW/SW SoC path.

VerilogSystemVerilogModelSimHW/SW co-design

electrical engineering / fpga systems

FPGA Digital Systems Design

FPGA and embedded systems work covering RTL modules, memory-mapped interfaces, simulation, and board-level validation on DE1-SoC hardware.

VerilogDE1-SoCQuartusembedded systems

downloads

lab pdfs and supporting files

downloadable reports and lab files stay here so the hardware track still links directly to the published material.