portfolio, case studies, and engineering work
electrical engineering / digital systems
AES-128 SoC Coprocessor
I built a memory-mapped AES-128 coprocessor with CBC and OFB support, verified it in simulation, and validated the HW/SW path against NIST test vectors.
highlights
- Defined a programmer-facing register map for keys, IVs, plaintext, and ciphertext transfer across the bus interface.
- Paired the RTL with embedded C running on the HPS so the project behaved like a usable SoC peripheral instead of an isolated block.
- Used simulation and hardware validation together to prove the design against real cipher-mode test vectors.
stack
evidence
role
RTL and integration designer for the AES coprocessor and its programmer-facing SoC interface.
problem
The coprocessor needed to behave like a usable SoC peripheral, not just a standalone RTL block, while supporting CBC and OFB verification flows.
ownership
I handled the RTL path, register-map thinking, the APB-style interface model, and end-to-end validation against embedded software and test vectors.
outcome
Implemented a 16 x 32-bit register model, validated CBC and OFB operation against NIST 800-38A vectors, and exercised the design through both simulation and DE1-SoC hardware.
artifact
Project summary and linked digital-systems archive covering the same RTL, interface, and hardware/software validation track.
Related digital-design lab material is linked above.